Method and apparatus for supporting verification of system, and computer product

ABSTRACT

In a verification support apparatus, an input unit accepts input of an unverified specification description representing an unverified design object constituted by unverified model elements. A searching unit searches, from verified specification descriptions representing verified design objects constituted by verified model elements, a verified specification description identical or similar to the unverified specification description input to the input unit based on the unverified model elements and the verified model elements. A logic-verification-content extracting unit extracts contents of logic verification performed on the verified design object, based on a result of search by the searching unit. An output unit outputs the contents of the logic verification extracted by the logic-verification-content extracting unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a technology for supportingverification in large-scale integration (LSI) design.

2. Description of the Related Art

In LSI design, when logic verification is performed for a design targetsystem constituted by hardware or software, generally, an experiencedworker such as a leader of each section estimates a logic verificationmethod, data and environments needed for the logic verification, andprocurement (development, purchase, and installation) costs thereofbased on experience, and a logic verification plan is determinedaccording to the estimation.

While it is essential to perform the logic verification operationverifying whether LSI operates properly and this logic verification isimportant to maintain a high quality especially for an LSI required tohave a large scale, a multifunction, a high speed, and low powerconsumption, higher efficiency in the operation by reducing a designperiod have been demanded. As LSI is made to have a large scale, amultifunction, a high speed, and low power consumption, types and scaleof a system to be a design target increases. Therefore, it isproblematic that cost of the logic verification increases as a whole. Asthe cost spent on the logic verification increases, it is problematicthat the risk increases when the costs of the logic verification aredifferent from the estimation of the experiment worker. Therefore, inLSI design, when the cost of the logic verification is increased and theassociated risk is generated, corresponding costs may be added to aproduct price and it is problematic that the price of LSI becomes highercompared to a case in which no increase in the cost of the logicverification occurs or no risk is generated.

To avoid this situation as much as possible, it may be considered tofind out information on the logic verification, such as how much work oflogic verification and how much cost are needed, from a great deal ofexperience in accordance with specifications of each design targetsystem to perform an operation for keeping the estimation error at aminimum. However, when trying to perform such an operation, since aburden of a designer is increased and the logic verification operationis disturbed, a labor amount is increased as a result, and it isproblematic that the logic verification operation is prolonged.

Generally, the information on the past logic verification is stored ineach section. Therefore, if logic verification of the system designed inone section is identical or similar to the past logic verificationperformed in the other section, the information on the logicverification in the other section cannot be diverted by a designer ofthe one section since it is very difficult to find the information.Thus, it is problematic that the information on the logic verificationcannot be shared between the sections.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least solve the aboveproblems in the conventional technology.

A verification support apparatus according to one aspect of the presentinvention includes an input unit configured to accept input of anunverified specification description representing an unverified designobject constituted by unverified model elements; a searching unitconfigured to search, from verified specification descriptionsrepresenting verified design objects constituted by verified modelelements, a verified specification description identical or similar tothe unverified specification description input to the input unit, basedon the unverified model elements and the verified model elements; alogic-verification-content extracting unit configured to extractcontents of logic verification performed on the verified design object,based on a result of search by the searching unit; and an output unitconfigured to output the contents of the logic verification extracted bythe logic-verification-content extracting unit.

A verification support method according to another aspect of the presentinvention includes inputting an unverified specification descriptionrepresenting an unverified design object described with unverified modelelements; searching, from verified specification descriptionsrepresenting verified design objects described with verified modelelements, a verified specification description identical or similar tothe unverified specification description input at the inputting, basedon the unverified model elements and the verified model elements;extracting contents of logic verification performed on the verifieddesign object, based on a result of search at the searching; andoutputting the contents of the logic verification extracted by thelogic-verification-content extracting unit.

A computer-readable recording medium according to still another aspectof the present invention stores therein a computer program for realizinga verification support method according to the above aspect.

The other objects, features, and advantages of the present invention arespecifically set forth in or will become apparent from the followingdetailed description of the invention when read in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a hardware configuration of averification support apparatus according to an embodiment of the presentinvention;

FIG. 2 is an explanatory diagram showing storage content of averification asset database according to the embodiment of the presentinvention;

FIG. 3 is a use case diagram of a verified system A;

FIG. 4 is a sequence diagram of the verified system A;

FIG. 5 is a layout diagram of the verified system A;

FIG. 6 is an explanatory diagram showing verification policies,verification items, and verification methods of the verified system A;

FIG. 7 is an explanatory diagram showing cost information of theverified system A;

FIG. 8 is an explanatory diagram showing a verification environment ofthe verified system A;

FIG. 9 is a use case diagram of a verified system B;

FIG. 10 is a sequence diagram of the verified system B;

FIG. 11 is a layout diagram of the verified system B;

FIG. 12 is an explanatory diagram showing a verification policy,verification items, and verification method of the verified system B;

FIG. 13 is an explanatory diagram showing cost information of theverified system B;

FIG. 14 is an explanatory diagram showing a verification environment ofthe verified system B;

FIG. 15 is a block diagram showing a functional configuration of theverification support apparatus according to the embodiment of thepresent invention;

FIG. 16 is a use case diagram of an unverified system X;

FIG. 17 is a sequence diagram of the unverified system X;

FIG. 18 is a layout diagram of the unverified system X;

FIG. 19 is an explanatory diagram showing an example of disassemblingtexts showing unverified model elements;

FIG. 20 is an explanatory diagram showing an example of disassemblingtexts showing verified model elements;

FIG. 21 is a chart showing a relationship between score conditions whenwords are compared and basic scores and associated scores in thosecases;

FIG. 22 is an explanatory diagram showing a relationship between theverified system A compared with the unverified system X and the scores;

FIG. 23 is an explanatory diagram showing a relationship between theverified system B compared with the unverified system X and the scores;

FIG. 24 is an explanatory diagram showing a relationship between theunverified system X and the verified systems A and B;

FIG. 25 is an explanatory diagram showing a search-result displayexample according to the embodiment of the verification supportapparatus of the present invention;

FIG. 26 is a sequence diagram of a verified system C;

FIG. 27 is a layout diagram of the verified system C;

FIG. 28 is an explanatory diagram showing a verified event group of theunverified system X when the specification description of the unverifiedsystem X is sequence diagram in UML;

FIG. 29 is an explanatory diagram showing a relationship with a verifiedmodel element of the verified system A and the score thereof;

FIG. 30 is an explanatory diagram showing a relationship with verifiedmodel elements of the verified system C and the scores thereof;

FIG. 31 is an explanatory diagram showing a verified model element groupof the unverified system X when the specification description of theunverified system X is a layout diagram in UML;

FIG. 32 is an explanatory diagram showing a relationship with verifiedmodel elements of the verified system A and the scores thereof;

FIG. 33 is an explanatory diagram showing a relationship with verifiedmodel elements of the verified system C and the scores thereof;

FIG. 34 is a flowchart (part 1) showing a verification supportprocessing of the verification support apparatus according to theembodiment of the present invention;

FIG. 35 is a flowchart (part 2) showing a verification supportprocessing of the verification support apparatus according to theembodiment of the present invention;

FIG. 36 is a flowchart (part 3) showing a verification supportprocessing of the verification support apparatus according to theembodiment of the present invention; and

FIG. 37 is a flowchart (part 4) showing a verification supportprocessing of the verification support apparatus according to theembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary embodiments according to the present invention will beexplained in detail below with reference to the accompanying drawings.

First, description will be made of a hardware configuration of theverification support apparatus according to the embodiment of thepresent invention. FIG. 1 is a block diagram showing a hardwareconfiguration of the verification support apparatus according to theembodiment of the present invention. As shown in FIG. 1, theverification support-apparatus includes a central processing unit (CPU)101, a read-only memory (ROM) 102, a random-access memory (RAM) 103, ahard disk drive (HDD) 104, a hard disk (HD) 105, a flexible disk drive(FDD) 106, a flexible disk (FD) 107 as an example of a removablerecording medium, a display 108, an interface (I/F) 109, a keyboard 110,a mouse 111, a scanner 112, and a printer 113. The components areconnected to each other through a bus 100.

The CPU 101 is responsible for overall control of the verificationsupport apparatus. The ROM 102 stores a program such as a boot program.The RAM 103 is used as a work area of the CPU 101. The HDD 104 controlsread/write of data from/to the HD 105 under a control of the CPU 101.The HD 105 stores data written under the control of the HDD 104.

The FDD 106 controls read/write of data from/to the FD 107 under acontrol of the CPU 101. The FD 107 stores data written under a controlof the FDD 106 and allows the verification support apparatus to read thedata stored in the FD 107.

Besides the FD 107, a removable recording medium may be a compact-diskread-only memory (CD-ROM) (a compact-disk recordable (CD-R), acompact-disk rewritable (CD-RW)), a magneto optical (MO) disk, a digitalversatile disk (DVD), and a memory card. The display 108 displays acursor, icons or tool boxes as well as data such as a document, animage, and function information. This display 108 may be, for example, acathode ray tube (CRT), a thin film transistor (TFT) liquid crystaldisplay, a plasma display, etc.

The I/F 109 is connected via a communication line to a network 114 suchas the internet and is connected to other apparatuses via this network114. The I/F 109 is responsible for interfacing the network 114 with theinside of the apparatus and controls input/output of data from/to anexternal apparatus. The I/F 109 may be, for example, a modem, a localarea network (LAN) adaptor, etc.

The keyboard 110 is provided with keys for entering characters, numericcharacters, various instructions, etc. to enter data. A touch-panelinput pad, a numeric keypad, etc. may be used instead. The mouse 111moves a cursor, selects an area or moves and resizes a window, etc. Atrackball or a joystick may be used instead, as long as similarfunctions for a pointing device are provided.

The scanner 112 optically reads an image and captures image data intothe verification support apparatus. The scanner 112 may have an OCRfunction. The printer 113 prints image data and document data. Theprinter 113 may be, for example, a laser printer or ink-jet printer.

Description will be made of storage content of a verification assetdatabase according to the embodiment of the present invention. FIG. 2 isan explanatory diagram showing the storage content of the verificationasset database according to the embodiment of the present invention. Asshown in FIG. 2, a verification asset database 200 includes a verifiedsystem name 201, a specification description content 202, and a logicverification content 203.

For the specification description, for example, the UML is applied, andthe verified system can store diagrams such as a use case diagram 221, asequence diagram 222, and a layout diagram 223 that are described in theUML. The logic verification content 203 is verification content of logicverification performed on the verified system. In the case of a verifiedsystem name “system A”, the verification content includes a verificationpolicy 231, a verification item 232, a verification method 233, costinformation 234, and a verification environment 235.

Description will be made of the storage content of the verified systemnamed “system A” stored in the verification asset database 200 shown inFIG. 2. FIG. 3 is a use case diagram of the verified system A; FIG. 4 isa sequence diagram of the verified system A; FIG. 5 is a layout diagramof the verified system A; FIG. 6 is an explanatory diagram showingverification policies, verification items, and verification methods ofthe verified system A; FIG. 7 is an explanatory diagram showing costinformation of the verified system A; and FIG. 8 is an explanatorydiagram showing a verification environment of the verified system A.

The use case diagram shown in FIG. 3 represents functions of the systemA. As shown in FIG. 3, an actor 301 is a verified model elementrepresenting a digital data input apparatus, which is an externalapparatus, and a use case 302 is a verified model element representing ause case description “input digital data” in the system A. A use case303 is a verified model element representing a use case description“write digital data” in the system A and an actor 304 is a verifiedmodel element representing a small computer system interface (SCSI)-HDapparatus, which is an external apparatus.

The sequence diagram shown in FIG. 4 represents data exchanges in thesystem A in chronological order. As shown in FIG. 4, at sequence number1, an event “data input (digital data)”, which is a verified modelelement, is performed by the actor 301 of the digital data inputapparatus toward an object 400 of the system A. At sequence number 1.1,an event “output to SCSI-HD (digital data)”, which is a verified modelelement, is performed by the object 400 of the system A toward the actor304 of the SCSI-HD apparatus.

The layout diagram shown in FIG. 5 represents a physical structure ofthe system A. As shown in FIG. 5, a node 501 is a verified model elementrepresenting the digital data input apparatus; a node 502 is a verifiedmodel element representing a micro processing unit (MPU); and a node 503is a verified model element representing the SCSI-HD apparatus. A link504 is a verified model element representing a bus connecting the node501 and the node 502, and a link 505 is a verified model elementrepresenting a SCSI connecting the node 502 and the node 503.

FIG. 6 illustrates a verification policy 601, a verification item 602,and a verification method 603 for each configuration of the system A.The verification policy 601 represents what technique should be used toperform logic verification. For example, for the SCSI-HD apparatus, itis defined that “assertion check of interface unit” should be performed.The verification item 602 represents details of verification content.For example, for the MPU, three verification items are listed, which are“SCSI access, BUS access, and initialization”. The verification method603 represents a technique when the logic verification was actuallyperformed. It is described that the logic verification of the digitaldata input apparatus was performed using “RTL simulation”.

FIG. 7 illustrates cost information representing costs spent on thelogic verification operation of the system A. Cost information 700includes an equipment cost, the number of process, required manpower,the number of logic bugs detected after release, the number ofrebuilding, etc. FIG. 8 illustrates a verification environment 800 whenthe logic verification operation of the system A was performed. Theverification environment 800 indicates tools used when the logicverification was performed on the verified system.

Description will be made of storage content of a verified system named“system B” stored in the verification asset database 200 shown in FIG.2. FIG. 9 is a use case diagram of the verified system B; FIG. 10 is asequence diagram of the verified system B; FIG. 11 is a layout diagramof the verified system B; FIG. 12 is an explanatory diagram showing averification policy, verification items, and a verification method ofthe verified system B; FIG. 13 is an explanatory diagram showing costinformation of the verified system B; and FIG. 14 is an explanatorydiagram showing a verification environment of the verified system B.

The use case diagram shown in FIG. 9 represents functions of theverified system B. As shown in FIG. 9, an actor 901 is a verified modelelement representing an national television standards committee (NTSC)signal pattern setting system, which is an external apparatus, and a usecase 902 is a verified model element representing a use case description“set NTSC signal pattern” in the system B. An actor 903 is a verifiedmodel element representing an NTSC signal generation control system,which is an external apparatus; a use case 904 is a verified modelelement representing a use case description “start NTSC signal output”in the system B; and a use case 905 is a verified model elementrepresenting a use case description “terminate NTSC signal output” inthe system B. A use case 906 is a verified model element representing ause case description “output NTSC signal” in the system B and an actor907 is a verified model element representing an NTSC signal inputsystem, which is an external apparatus.

The sequence diagram shown in FIG. 10 represents data exchanges in thesystem B in chronological order. As shown in FIG. 10, at sequence number1, an event “set NTSC signal pattern”, which is a verified modelelement, is performed by the actor 901 of the NTSC signal patternsetting system toward an object 1000 of the system B. At sequence number2, an event “start signal generation”, which is a verified modelelement, is performed by the actor 903 of the NTSC signal generationcontrol system toward the object 1000 of the system B. At sequencenumber 2.1, an event “signal generation”, which is a verified modelelement, is performed by the object 1000 of the system B toward theactor 907 of the NTSC signal input system. At sequence number 3, anevent “terminate signal generation”, which is a verified model element,is performed by the actor 903 of the NTSC signal generation controlsystem toward the object 1000 of the system B.

The layout diagram shown in FIG. 11 represents a physical structure ofthe verified system B. As shown in FIG. 11, a node 1101 represents theNTSC signal pattern setting system; a node 1102 is a verified modelelement representing the NTSC signal generation control system; a node1103 is a verified model element representing an NTSC signal outputsystem, which is the system B; and a node 1104 is a verified modelelement representing the NTSC signal input system. A link 1105 is averified model element representing a signal cable connecting the node1101 and the node 1102; a link 1106 is a verified model elementrep-resenting a signal cable connecting the node 1102 and the node 1103;and a link 1107 is a verified model element representing a signal cableconnecting the node 1103 and the 1104;

FIG. 12 illustrates a verification policy 1201, verification items 1202,and a verification method for the NTSC signal output system, which isthe system B. FIG. 13 illustrates cost information 1300 representingcosts spent on the logic verification operation of the system B. FIG. 14illustrates a verification environment 1400 when the logic verificationoperation of the system B was performed.

Description will be made of a functional configuration of theverification support apparatus according to the embodiment of thepresent invention. FIG. 15 is a block diagram showing a functionalconfiguration of the verification support apparatus according to theembodiment of the present invention. As shown in FIG. 15, a verificationsupport apparatus 1500 includes a storing unit 1501, an input unit 1502,a searching unit 1503, a logic-verification-content extracting unit1504, and an output unit 1505.

The storing unit 1501 stores the UML describing a system verified byperforming the logic verification, and the logic verification contentthereof. The storing unit 1501 includes the verification asset database200. The storing unit 1501 may be configured to be provided in theverification support apparatus 1500 and may be configured to be providedin a not-shown external server via the network 114 shown in FIG. 1, suchas the internet, a LAN, a wide area network (WAN), etc. Specifically,for example, the function of the storing unit 1501 is realized by theROM 102, the RAM 103, the HD 105, the FD 107, etc. shown in FIG. 1.

The input unit 1502 accepts input of an unverified specificationdescription representing an unverified design object, which is describedwith unverified model elements. The unverified design object can be theunverified system X on which the logic verification has not beenperformed described above. The specification description can be the UMLrepresenting a function, a processing, a structure, etc. of a designobject or a diagram represented by the UML. Specifically, for example,the specification description can be expressed by diagrams such as theuse case diagram, the sequence diagram, and the layout diagram in theUML described above.

The model element is a diagram, a symbol, a word, a text, or a groupthereof constituting the specification description for representing thedesign object, and if the UML is used for the specification description,the model element can represent an actor, a use case, a class, anobject, an event, a guard condition, a node, a link, etc.

Description will be made of the unverified specification descriptioninput by the input unit 1502 with reference to FIGS. 16 to 18. FIG. 16is a use case diagram of the unverified system X; FIG. 17 is a sequencediagram of the unverified system X; and FIG. 18 is a layout diagram ofthe unverified system X.

The use case diagram shown in FIG. 16 represents functions of the systemX. As shown in FIG. 16, an actor 1601 is a model element representing anNTSC image input apparatus, which is an external apparatus, and a usecase 1602 is a model element describing a use case description “inputNTSC image” in the system X. An actor 1603 is a model elementrepresenting a PAL image input apparatus, which is an externalapparatus, and a use case 1604 is a model element describing a use casedescription “input PAL image” in the system X. A use case 1605 is amodel element describing a use case description “write digital data” inthe system X, and an actor 1606 is a model element representing anSCSI-HD apparatus, which is an external apparatus.

The sequence diagram shown in FIG. 17 represents data exchanges in thesystem X in chronological order. As shown in FIG. 17, at sequence number1, an event “signal input” constituting a model element is performed bythe actor 1601 of the NTSC image input apparatus toward an object 1700of the system X. At sequence number 1.1, an event “convert into digitaldata (input signal)” constituting a model element is performed in theobject 1700 of the system X. At sequence number 1.2, an event “output toSCSI-HD (digital data)” constituting a model element is performed by theobject 1700 of the system X toward the actor 1606 of the SCSI-HDapparatus.

The layout diagram shown in FIG. 18 represents a physical structure ofthe system X. As shown in FIG. 18, a node 1801 is a model elementrepresenting the NTSC image input apparatus; a node 1802 is a modelelement representing the PAL image input apparatus; a node 1803 is amodel element representing MPU; and a node 1804 is a model elementrepresenting the SCSI-HD apparatus. A link 1805 is a model elementrepresenting a bus connecting the node 1801 and the node 1803, and alink 1806 is a model element representing a bus connecting the node 1802and the node 1803. A link 1807 is a model element representing a SCSIconnecting the node 1803 and the node 1804.

As shown in FIG. 15, the searching unit 1503 searches a verifiedspecification description identical or similar to the unverifiedspecification description input by the input unit 1502 from the verifiedspecification descriptions representing the verified design objectsdescribed with the verified model elements, based on the unverifiedmodel elements and the verified model elements. The identity,similarity, or non-similarity between the unverified specificationdescription and the verified specification description can berepresented by converting into a numerical value using the number ofmatches between the unverified model elements and the verified modelelements, or a score for scoring the number of the matches. When the UMLof an unused specification description is input, for example, if the UMLis written in the form of a use case diagram, the searching unit 1503can search the UML of a use case diagram identical or similar to theinput use case diagram from the storing unit 1501. The internalmechanism of the searching unit 1503 will be described later.

The logic-verification-content extracting unit 1504 extracts content ofthe logic verification performed on the verified system searched by thesearching unit 1503, that is, the verification policy 231, theverification item 232, the verification method 233, the cost information234, and the verification environment 235 shown in FIG. 2 from thestoring unit 1501. The output unit 1505 outputs the logic verificationcontent extracted by the logic-verification-content extracting unit1504. The functions of the input unit 1502, the searching unit 1503, thelogic-verification-content extracting unit 1504, and the output unit1505 are realized, specifically, by executing programs recorded on, forexample, the ROM 102, the RAM 103, the HD 105, the FD 107 shown in FIG.1, etc. with the CPU 101, or by the I/F 109.

Description will be made of the internal mechanism of the searching unit1503. As shown in FIG. 15, the searching unit 1503 includes anunverified-model-element extracting unit 1511, a verified-model-elementextracting unit 1512, a processing unit 1513, and a similaritycalculating unit 1514.

The unverified-model-element extracting unit 1511 extracts theunverified model element from the unverified specification descriptioninput by the input unit 1502. For example, when the use case diagramshown in FIG. 16 is input, the unverified-model-element extracting unit1511 extracts an unverified model element X1 “input NTSC image”, anunverified model element X2 “input PAL image”, and an unverified modelelement X3 “write digital data”, which are the use case descriptionsdescribed in this use case diagram.

The verified-model-element extracting unit 1512 extracts the verifiedmodel element from the verified specification description stored in thestoring unit 1501 when the unverified specification description is inputby the input unit 1502. For example, in the case of the verified systemA, when the use case diagram is input to the input unit 1502, theverified-model-element extracting unit 1512 extracts an unverified modelelement A1 “input digital data”, which is the use case description shownin FIG. 3, and an unverified model element A2 “write digital data”,which is the use case description. The extraction of the verified modelelement can be performed for all the verified specification descriptionsstored in the storing unit 1501.

The processing unit 1513 processes each of the unverified model elementand the verified model element. The processing unit 1513 includes adisassembling unit 1515 and a group generating unit 1516. Thedisassembling unit 1515 performs disassembly when the input UML is a usecase diagram. The group generating unit 1516 generates an event group ora layout group described later when the input UML is a sequence diagramor a layout diagram.

The disassembling unit 1515 disassembles each of a use case descriptionof a text indicating the unverified model element extracted by theunverified-model-element extracting unit 1511 and a use case descriptionof a text indicating the verified model element extracted by theverified-model-element extracting unit 1512 into words. In the wordsobtained by the disassembling unit 1515, only nouns and verbs areutilized, and words indicating particles such as “ga”, “ha”, “ni”, “he”,“wo”, etc. are erased. FIG. 19 is an explanatory diagram showing anexample of disassembling texts indicating the unverified model elements,and FIG. 20 is an explanatory diagram showing an example ofdisassembling texts indicating verified model elements.

As shown in FIG. 19, for example, in the case of the unverified modelelement X1 “input NTSC image (NTSC-gazou wo nyuuryoku-suru)”, thedisassembling unit 1515 divides this text into words and disassemblesthe text into “NTSC image (NTSC-gazou)”, “(wo)”, and “input(nyuuryoku-suru)”. A word “wo” is erased because the word is a particle,and “NTSC image (NTSC-gazou)” and “input (nyuuryoku-suru)” are used. Asshown in FIG. 20, in the case of the verified model element A1 “inputdigital data (digital-data wo nyuuryoku-suru)”, the disassembling unit1515 divides this text into words and disassembles the text into“digital data (digital-data)”, “(wo)”, and “input (nyuuryoku-suru)”. Aword “wo” is erased because the word is a particle, and “digital data(digital-data)” and “input (nyuuryoku-suru)” are used. The disassembledwords can be weighted by a weight setting unit 1517. For example, bygiving a basic score “+1” to the word “input”, a word desired to befocused may be weighted.

When an unverified sequence diagram is input, the group generating unit1516 generates an event group from events indicating the unverifiedmodel elements extracted by the unverified-model-element extracting unit1511. Similarly, the group generating unit 1516 generates an event groupfrom events showing the verified model elements extracted by theverified-model-element extracting unit 1512. A specific example of theevent group will be described later.

When an unverified layout diagram is input, the group generating unit1516 generates a layout group from the nodes and the links indicatingthe unverified model elements extracted by the unverified-model-elementextracting unit 1511. Similarly, the group generating unit 1516generates a layout group from the nodes and the links indicating theverified model elements extracted by the verified-model-elementextracting unit 1512. A specific example of the layout group will alsobe described later.

The similarity calculating unit 1514 calculates a similarity between theunverified model element extracted by the unverified-model-elementextracting unit 1511 and the verified model element extracted by theverified-model-element extracting unit 1512. Specifically, thesimilarity calculating unit 1514 includes a comparing unit 1518 and ascore calculating unit 1519.

The comparing unit 1518 compares the unverified model element extractedby the unverified-model-element extracting unit 1511 and the verifiedmodel element extracted by the verified-model-element extracting unit1512. Specifically, when an UML use case diagram is input by the inputunit 1502, the comparison is performed based on the words obtained bythe disassembling unit 1515. For example, when comparing the unverifiedmodel element X1 shown in FIG. 19 and the verified model element A1shown in FIG. 20, the word “NTSC image” of the unverified model elementX1 is not identical to the word “digital data” in the verified modelelement A1. On the other hand, the word “input” of the unverified modelelement X1 is identical to the word “input” in the verified modelelement A1. In this case, a part of the model elements X1, and A1 areidentical. When comparing the unverified model element X3 and theverified model element A2, the word “digital data” of the unverifiedmodel element X3 is identical to the word “digital data” in the verifiedmodel element A2. Similarly, the word “write” of the use casedescription X3 is identical to the word “write” in the verified modelelement A1. In this case, the model elements X3, and A2 are completelyidentical.

The score calculating unit 1519 calculates a score representing thesimilarity between the unverified model element and the verified modelelement based on the result of the comparison performed by the comparingunit 1518. FIG. 21 is a chart showing a relationship between scoreconditions when words are compared, and basic scores and associatedscores in those cases. The basic score is a score added or multipliedwhen comparing the unverified model element and the verified modelelement. The associated score is a score additionally added when acertain condition is satisfied in the comparison by the comparing unit1518. The score represents a degree of similarity to an unverifiedsystem for each verified system, and a designer can determine that thesystems are not similar when the score is a predetermined value or lessand that the systems are similar when the score is greater than thepredetermined value. In the scores of the verified systems, the systemsranked in the top k can be determined to be similar and the systemsranked at k+1 or lower can be determined to be not similar. The verifiedsystem with the highest score is most similar to the unverified system.

Description will be made of a relationship between the verified systemcompared with the unverified system X and the scores. FIG. 22 is anexplanatory diagram showing a relationship between the verified system Acompared with the unverified system X and the scores. FIG. 23 is anexplanatory diagram showing a relationship between the verified system Bcompared with the unverified system X and the scores.

Referring to FIGS. 22 and 23, each of verified model elements A1 and A2,and B1 to B4 is compared with each of the unverified model elements X1to X3 to obtain a score calculated by the score calculating unit 1519.

For example, with regard to the verified model element A1 shown in FIG.22, when compared with the unverified model element X1, the word“digital data” of the verified model element A1 is identical to the word“digital data” of the unverified model element X1, which corresponds to“when word is identical” shown in FIG. 21, and the basic score “1” isadded. On the other hand, since the word is not identical to the wordsof the unverified model elements X2 and X3, the basic score is notadded. Therefore, the basic score of the word “digital data” of theverified model element A1 is “1”.

With regard to the verified model element A1 shown in FIG. 22, whencompared with the unverified model element X1, the word “input” of theverified model element A1 is identical to the word “input” of theunverified model element X1, which corresponds to “when word isidentical” in the chart shown in FIG. 21, and the basic score “1” isadded. Similarly, when compared with the unverified model element X2,the word “input” of the verified model element A1 is identical to theword “input” of the unverified model element X1, which corresponds to“when word is identical” shown in FIG. 22, and the basic score “1” isadded. On the other hand, since the word is not identical to the wordsof the unverified model element X3, the basic score is not added.Therefore, the basic score of the word “input” of the verified modelelement A1 is “2”.

Since the verified model element A1 does not satisfy the score conditionfor adding the associated score shown in FIG. 21, the associated scoreis “0”. Therefore, a score subtotal of the basic score and theassociated score is “3”.

With regard to the verified model element A2 shown in FIG. 22, whencompared with the unverified model element X3, the word “digital data”of the verified model element A2 is identical to the word “digital data”of the unverified model element X3, which corresponds to “when word isidentical” in the chart shown in FIG. 21, and the basic score “1” isadded. Similarly, the word “write” of the verified model element A2 isidentical to the word “write” of the unverified model element X3, whichcorresponds to “when word is identical” shown in the chart of FIG. 21,and the basic score “1” is added.

Since the verified model element A2 satisfies the score condition “whenall words in one unverified model element are identical” for adding theassociated score shown in FIG. 21, the associated score can be added.Since the total number of the words is n=2, the associated number to beadded is “2”. Therefore, for the verified model element A2, a scoresubtotal of the basic score and the associated score is “4”.

Thus, the score indicating the similarity of the verified system A tothe unverified system X is a total value of the score subtotal values ofthe verified model elements A1 and A2, which is “7”.

If the verified model elements B1 to B4 shown in FIG. 23 are comparedwith the unverified model elements X1 and X2, since no word isidentical, the score conditions in the chart shown in FIG. 21 are notsatisfied. Therefore, the score indicating the similarity of theverified system B to the unverified system X is “0”.

Description will be made of a relationship between the unverified systemX and the verified systems A and B. FIG. 24 is an explanatory diagramshowing a relationship between the unverified system X and the verifiedsystems A and B. A thin lines for connecting the unverified system X andthe verified systems A and B shown in FIG. 24 indicate that theunverified model element and the verified model element are partiallyidentical, and a thick line indicates that the unverified model elementand the verified model element are completely identical. In an exampleshown in FIG. 24, although the unverified model elements X1 to X3 arepartially identical to the verified model element A1, therefore, linkedwith the thin lines to the verified model element A1, the associatedscore is “0” because the model elements are not completely identical. Onthe other hand, since the unverified model element X3 and the verifiedmodel element A2 are completely identical, the associated score is “2”as shown in FIG. 21.

On the other hand, since the unverified model elements X1 to X3 are notidentical to any of the verified model elements B1 to B4, the unverifiedmodel elements X1 to X3 are not linked with the thick line nor the thinline. Therefore, it is found also from this figure that the system B hasthe score indicating the similarity of “0” and is not similar to thesystem X.

Description will be made of a search-result display example according tothe embodiment of the verification support apparatus of the presentinvention. FIG. 25 is an explanatory diagram showing a search-resultdisplay example according to the embodiment of the verification supportapparatus of the present invention. A search screen 2500 as shown inFIG. 25 is displayed on the display shown in FIG. 1. The search screen2500 can be output also by the printer 113. The search screen 2500 has aframe 2501, a frame 2502, and a frame 2503. The frame 2501 displays asearch result, which is a name of the searched system with the highestscore indicating the similarity and the score thereof. The frame 2502displays a search result list 2504. In the search result list 2504,names of the verified systems are displayed in the order of descendingscores indicating the similarity. The frame 2503 displays a searchresult, which is a verification policy 2505, a verification item 2506, averification method 2507, cost information 2508, and a verificationenvironment 2509 of the searched system having the highest scoreindicating the similarity.

Description will be made of an example when the use case diagram of theverified system is identical and when the sequence diagram and thelayout diagram are different. FIG. 26 is a sequence diagram of averified system C, and FIG. 27 is a layout diagram of the verifiedsystem C. A use case diagram of this verified system C is identical tothe use case diagram of the verified system A shown in FIG. 3 andomitted.

The sequence diagram shown in FIG. 26 represents data exchanges in theverified system C in chronological order. As shown in FIG. 26, atsequence number 1, an event “data input (digital data)” constituting averified model element is performed by the actor 301 of the digital datainput apparatus toward an object 2601 of a control ASIC. At sequencenumber 1.1, an event “write (digital data)” constituting a verifiedmodel element is performed by the object 2601 of the control ASIC towardan object 2602 of a RAM. At sequence number 1.2, an event “read ( )”constituting a verified model element is performed by the object 2601 ofthe control ASIC toward the object 2602 of the RAM. A guard condition atthis point is [RAM is FULL]. At sequence number 1.3, an event “write toSCSI (digital data)” constituting a verified model element is performedby the object 2601 of the control ASIC toward an object 2603 of aSCSI-controller. A guard condition at this point is [RAM is FULL]. Atsequence number 1.3.1, an event “output to SCSI-HD (digital data)”constituting a verified model element is performed by the object 2603 ofthe SCSI-controller toward the actor 304 of a SCSI-HD apparatus.

The layout diagram shown in FIG. 27 represents a physical structure ofthe system C. As shown in FIG. 27, a node 2701 is a verified modelelement representing the control application specific integrated circuit(ASIC); a node 2702 is a verified model element representing the RAM;and a node 2703 is a verified model element representing theSCSI-controller. A link 2704 is a verified model element representing acontrol interface connecting the node 501 and the node 2702; a link 2705is a verified model element representing a RAM interface connecting thenode 2701 and the node 2702; a link 2706 is a verified model elementrepresenting a SCSI control interface coupling the node 2701 and thenode 2703; and a link 2707 is a verified model element representing aSCSI connecting the node 2703 and the node 503.

Description will be made of a relationship with the verified modelelements of the verified systems A and C, and the scores thereof whenthe description content of the specification description of theunverified system X is the UML sequence diagram. FIG. 28 is anexplanatory diagram showing a verified event group of the unverifiedsystem X when the specification description of the unverified system Xis the UML sequence diagram; FIG. 29 is an explanatory diagram showing arelationship with the verified model element of the verified system Aand the score thereof; and FIG. 30 is an explanatory diagram showing arelationship with the verified model elements of the verified system Cand the scores thereof.

An unverified model element group X1 shown in FIG. 28 is an event groupcombining the event “signal input” at sequence number 1 and the event“convert into digital data (input signal)” at sequence number 1.1 shownin FIG. 17. An unverified model element group X12 is an event groupcombining the event “convert into digital data (input signal)” atsequence number 1.1 and the event “output to SCSI-HD (digital data)” atsequence number 1.2.

A verified model element group A11 shown in FIG. 29 is an event groupcombining the event “data input (digital data)” at sequence number 1 andthe event “output to SCSI-HD (digital data)” at sequence number 1.1shown in FIG. 4. When comparing the verified model element group A11 andthe an verified model element group X11, as shown in FIG. 21, since onlythe event “output to SCSI-HD (digital data)” is identical: the basicscore is “1”, the associated score is “0”; and the total score is “1”.When comparing the verified model element groups C11 to C14 and theunverified model element group X11, as shown in FIG. 21, the subtotalscores are “0” for the verified model element groups C11 to C13, andsince only the event “output to SCSI-HD (digital data)” is identical andthe guard condition “[RAM is FILL]” is present for the event group C14:the basic score is “0.5”; the associated score is “0”; and the subtotalscore is “0.5”. Therefore, the total score for the verified system C is“0.5”. Thus, with regard to the data flow in the system, it is foundthat the verified system C is more similar to the system X than theverified system A.

Description will be made of a relationship with the verified modelelements of the verified systems A and C, and the scores thereof whenthe description content of the specification description of theunverified system X is the UML layout diagram. FIG. 31 is an explanatorydiagram showing the verified model element groups of the unverifiedsystem X when the specification description of the unverified system Xis the UML layout diagram; FIG. 32 is an explanatory diagram showing arelationship with the verified model elements of the verified system Aand the scores thereof; and FIG. 33 is an explanatory diagram showing arelationship with the verified model elements of the verified system Cand the scores thereof.

Unverified model element groups shown in FIG. 31 are layout groups andare model element groups combining the nodes and the links connected inthe layout diagram shown in FIG. 5. An unverified model element groupX21 is a layout group combining the node 1801 and the link 1805 shown inFIG. 18; an unverified model element group X22 is a layout groupcombining the node 1802 and the link 1806 shown in FIG. 18; anunverified model element group X23 is a layout group combining the node1803 and the link 1807 shown in FIG. 18; and an unverified model elementgroup X24 is a layout group combining the link 1807 and the node 1804shown in FIG. 18.

Referring to FIG. 32, a verified model element group A21 of the verifiedsystem A is a layout group combining the node 501 and the link 504 shownin FIG. 5; a verified model element group A22 is a layout groupcombining the node 502 and the link 504 shown in FIG. 5; and a verifiedmodel element group A23 is a layout group combining the node 502 and thelink 505 shown in FIG. 5.

When comparing the verified model element groups A21 to A24 of thesystem A with the unverified model element groups X21 to X25 of thesystem X shown in FIG. 31, since the verified model element group A21 isnot identical to any of the unverified model element groups X21 to X25,the basic score is “0”.

Since the verified model element group A22 is identical to theunverified element group X23, the basic score is “1”. Since the verifiedmodel element group A23 is identical to the unverified element groupX24, the basic score is “1”. Since the verified model element group A24is identical to the unverified element group X25, the basic score is“1”. Therefore, the total score of the verified system A is “3”.

Referring to FIG. 33, a verified model element group C21 of the verifiedsystem C is a layout group combining the node 501 and the link 2704shown in FIG. 27; a verified model element group C22 is a layout groupcombining the link 2704 and the node 2701 shown in FIG. 27; a verifiedmodel element group C23 is a layout group combining the node 2701 andthe link 2705 shown in FIG. 27; a verified model element group C24 is alayout group combining the link 2705 and the node 2702 shown in FIG. 27;a verified model element group C25 is a layout group combining the node2701 and the link 2706 shown in FIG. 27; a verified model element groupC26 is a layout group combining the link 2706 and the node 2703 shown inFIG. 27; a verified model element group C27 is a layout group combiningthe node 2703 and the link 2707 shown in FIG. 27; and a verified modelelement group C28 is a layout group combining the link 2707 and the node503 shown in FIG. 27.

When comparing the verified model element groups C21 to C28 of thesystem C with the unverified model element groups X21 to X25 of thesystem X shown in FIG. 31, since the verified model element groups C21to C27 are not identical to any of the unverified model element groupsX21 to X25, the basic score is “₀”. On the other hand, since theverified model element group C28 is identical to the unverified modelelement group X25, the basic score is “1”. Therefore, the total score ofthe verified system C is “1”. Thus, with regard to the hardwareconfiguration of the system, the verified system A is more similar tothe system X than the unverified system C.

Description will be made of a verification support processing by theverification support apparatus according to the embodiment of thepresent invention. FIGS. 34 to 37 are flowcharts showing theverification support processing by the verification support apparatusaccording to the embodiment of the present invention. As shown in FIG.34, if the UML of the unverified system is input (step S3401: YES), itis determined whether the input UML is the use case diagram (stepS3402). If the UML is not the use case diagram (step S3402: NO), it isdetermined whether the input UML is the sequence diagram (step S3403).If the UML is not the sequence diagram (step S3403: NO), it isdetermined whether the input UML is the layout diagram (step S3404). Ifthe UML is not the layout diagram (step S3404: NO), the procedure goesback to step S3402.

If the input UML is the use case diagram (step S3402: YES), as shown inFIG. 35, the unverified model elements are extracted from the input usecase diagram (step S3501). The texts showing the extracted unverifiedmodel elements are disassembled by the disassembling unit 1515 intowords (step S3502), and i=1 is established (step S3503). It is searchedin the storing unit 1501 whether the use case diagram of the i-thverified system is present (step S3504). If the use case diagram is notpresent (step S3504: NO), i is incremented by one (step S3505) and theprocedure goes back to step S3504.

If the use case diagram of the i-th verified system is present (stepS3504: YES), the use case diagram of the i-th verified system isextracted from the storing unit 1501 (step S3506). The verified modelelements are extracted from the extracted use case diagram (step S3507),and the texts thereof are disassembled into words (step S3508).

The unverified model elements are compared with the verified modelelements (step S3509). The comparison is performed between the wordsobtained by disassembling. Based on the comparison result, a score ofthe i-th verified system is calculated (step S3510). If i is not equalto the total number N of the verified systems stored in the storing unit1501 (step S3511: NO), i is incremented by one (step S3512) and theprocedure goes back to step S3504.

On the other hand, if i is equal to the total number N of the verifiedsystems stored in the storing unit 1501 (step S3511: YES), the logicverification content of the verified system having the highest score isextracted from the storing unit 1501 (step S3513). The extracted logicverification content is output (step S3514) and displayed on the display108.

If the input UML is the sequence diagram (step S3403: YES) in FIG. 34,the unverified model elements are extracted from the input sequencediagram (step S3601) as shown in FIG. 36. One event group is formed fromunverified model elements with consecutive sequence numbers (step S3602)and i=1 is established (step S3603). It is searched in the storing unit1501 whether the sequence diagram of the i-th verified system is present(step S3604). If the sequence diagram is not present (step S3604: NO), iis incremented by one (step S3605) and the procedure goes back to stepS3604.

If the sequence diagram of the i-th verified system is present (stepS3604: YES), the sequence diagram of the i-th verified system isextracted from the storing unit 1501 (step S3606). The verified modelelements are extracted from the extracted sequence diagram (step S3607),and one event group is formed from the verified model elements withconsecutive sequence numbers (step S3608).

The unverified model elements and the verified model elements formingthe event groups are compared (step S3609). Based on the comparisonresult, a score of the i-th verified system is calculated (step S3610).If i is not equal to the total number N of the verified systems storedin the storing unit 1501 (step S3611: NO), i is incremented by one (stepS3612, and the procedure goes back to step S3604.

On the other hand, If i is equal to the total number N of the verifiedsystems stored in the storing unit 1501 (step S3611: YES), the logicverification content of the verified system having the highest score isextracted from the storing unit 1501 (step S3613). The extracted logicverification content is output (step S3614) and displayed on the display108.

If the input UML is the layout diagram (step S3404: YES) in FIG. 34, theunverified model elements are extracted from the input layout diagram(step S3701) as shown in FIG. 37. One layout group is formed from theunverified model element groups with consecutive sequence numbers (stepS3702), and i=1 is established (step S3703). It is searched in thestoring unit 1501 whether the layout diagram of the i-th verified systemis present (step S3704). If the layout diagram is not present (stepS3704: NO), i is incremented by one (step S3705), and the procedure goesback to step S3704.

If the layout diagram of the i-th verified system is present (stepS3704: YES), the layout diagram of the i-th verified system is extractedfrom the storing unit 1501 (step S3706). The nodes and linksconstituting the verified model elements are extracted from theextracted layout diagram (step S3707), and one layout group is formedfrom the consecutive connected nodes and links (step S3708).

The unverified model elements and the verified model elements formingthe layout groups are compared (step S3709). Based on the comparisonresult, a score of the i-th verified system is calculated (step S3710).If i is not equal to the total number N of the verified systems storedin the storing unit 1501 (step S3711: NO), i is incremented by one (stepS3712), and the procedure goes back to step S3704.

On the other hand, if i is equal to the total number N of the verifiedsystems stored in the storing unit 1501 (step S3711: YES), the logicverification content of the verified system having the highest score isextracted from the storing unit 1501 (step S3713). The extracted logicverification content is output (step S3714) and displayed on the display108.

Thus, in accordance with the input UML diagrams, the similarity betweenthe unverified UML and the verified UML can be calculated by convertinginto a score, and the content of the logic verification performed forthe verified system having the highest similarity can be offered to thedesigner.

Although the UML description of the specification description isdescribed using the use case diagrams, the sequence diagrams, and thelayout diagrams in the above embodiment, class diagrams, objectdiagrams, collaboration diagrams, state chart diagrams, activitydiagrams, package diagrams, or component diagrams may also be used.

Although the verified specification description and the logicverification content thereof are stored in the storing unit 1501 in theabove embodiment, unverified common specific description and logicverification content thereof may be stored. When an unverified designobject is input, the name thereof may be input.

As described above, according to the verification support apparatus ofthe embodiment, the costs of the logic verification performed on thesystem to be designed can be reduced. Consequently, the loss that iscaused when the cost estimation of the logic verification is incorrectcan also be reduced. Therefore, with the reduction of the costs and lossof the logic verification, inexpensive LSI can be supplied to themarket.

Since it is not necessary for the designer does to perform all the costestimation required for the logic verification operation, the burden onthe designer can be reduced, and therefore, the labor and the workingperiod of the logic verification operation can be reduced.

The logic verification content stored in each section can be sharedamong sections. Therefore, the design assets can be diverted, and thelabor and the working period of the logic verification operation can bereduced.

While in a conventional practice, a skilled worker such as a sectionleader performs the estimation of the logic verification costs, withthis verification support apparatus, also an individual other than theskilled worker can easily perform the estimation of the logicverification costs.

The verification support method described in the embodiment can beachieved by executing a program prepared in advance with a computer suchas a personal computer and a workstation. The program is recorded on acomputer-readable recording medium, such as a HD, an FD, a CD-ROM, anMO, and a DVD, and is read from the recording medium by the computer forexecution. The program may be a transmission medium that can bedistributed through network such as the internet.

As described above, according to the present invention, the verifieddesign object can be identified which is designed in accordance with thespecification description approximated to the specification descriptionof the unverified design object, and the content of the logicverification performed on the verified design object can be obtained.Thus, the costs of the logic verification operation can be reduced andthe operation time can be shortened.

Although the invention has been described with respect to a specificembodiment for a complete and clear disclosure, the appended claims arenot to be thus limited but are to be construed as embodying allmodifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

1. A verification support apparatus, comprising: an input unitconfigured to accept input of an unverified specification descriptionrepresenting an unverified design object constituted by unverified modelelements; a searching unit configured to search, from verifiedspecification descriptions representing verified design objectsconstituted by verified model elements, a verified specificationdescription identical or similar to the unverified specificationdescription input to the input unit, based on the unverified modelelements and the verified model elements; a logic-verification-contentextracting unit configured to extract contents of logic verificationperformed on the verified design object, based on a result of search bythe searching unit; and an output unit configured to output the contentsof the logic verification extracted by the logic-verification-contentextracting unit.
 2. The verification support apparatus according toclaim 1, wherein the searching unit includes an unverified-model-elementextracting unit configured to extract the unverified model elements; averified-model-element extracting unit configured to extract theverified model elements; and a similarity calculating unit configured tocalculate a similarity between the unverified model element extracted bythe unverified-model-element extracting unit and the verified modelelement extracted by the verified-model-element extracting unit, and thelogic-verification-content extracting unit is configured to extract thecontents of the logic verification performed on the verified designobject based on the similarity calculated by the similarity calculatingunit.
 3. The verification support apparatus according to claim 2,wherein the similarity calculating unit includes a comparing unitconfigured to compare a text expressing the unverified model elementextracted by the unverified-model-element extracting unit and a textexpressing the verified model element extracted by theverified-model-element extracting unit; and a score calculating unitconfigured to calculate a score representing the similarity based on aresult of comparison by the comparing unit, and thelogic-verification-content extracting unit is configured to extract thecontents of the logic verification performed on the verified designobject, based on the score calculated by the score calculating unit. 4.The verification support apparatus according to claim 3, wherein thesimilarity calculating unit further includes a disassembling unitconfigured to disassemble each of the text expressing the unverifiedmodel element extracted by the unverified-model-element extracting unitand the text expressing the verified model element extracted by theverified-model-element extracting unit into words, and the comparingunit is configured to compare the text expressing the unverified modelelement extracted by the unverified-model-element extracting unit andthe text expressing the verified model element extracted by theverified-model-element extracting unit, based on the words obtained bydisassembling by the disassembling unit.
 5. The verification supportapparatus according to claim 4, further comprising a weight setting unitconfigured to weight the words obtained by disassembling the textexpressing the unverified model element by the disassembling unit,wherein the score calculating unit is configured to calculate the scorerepresenting the similarity based on the result of comparison by thecomparing unit and the weight of the word weighted by the weight settingunit.
 6. The verification support apparatus according to claim 1,wherein the unverified specification description representing theunverified design object and the verified specification descriptionrepresenting the verified design object are described in a unifiedmodeling language.
 7. The verification support apparatus according toclaim 1, wherein the contents of the logic verification includes atleast any one of a logic verification policy, an item of the logicverification, a logic verification method, information on cost requiredfor the logic verification, and a tool used when the logic verificationis performed on the verified design object.
 8. A verification supportmethod, comprising: inputting an unverified specification descriptionrepresenting an unverified design object described with unverified modelelements; searching, from verified specification descriptionsrepresenting verified design objects described with verified modelelements, a verified specification description identical or similar tothe unverified specification description input at the inputting, basedon the unverified model elements and the verified model elements;extracting contents of logic verification performed on the verifieddesign object, based on a result of search at the searching; andoutputting the contents of the logic verification extracted by thelogic-verification-content extracting unit.
 9. A computer-readablerecording medium that stores therein a verification support programmaking a computer execute: inputting an unverified specificationdescription representing an unverified design object described withunverified model elements; searching, from verified specificationdescriptions representing verified design objects described withverified model elements, a verified specification description identicalor similar to the unverified specification description input at theinputting, based on the unverified model elements and the verified modelelements; extracting contents of logic verification performed on theverified design object, based on a result of search at the searching;and outputting the contents of the logic verification extracted by thelogic-verification-content extracting unit.